Stacking wafers, dies or chips, and the formation of multi-die package with dense interconnection are methods to provide increased density in an electronic system. Such three-dimensional (3D) integrated circuits and dense package interconnections can include chips manufactured via different technologies or processes, without the need to modify the manufacturing process used for each chip. Thermal and physical stresses can result at the connection points between chips in a 3D integrated circuit or dense multi-die packages. As a result, the interface used between such chips is essential to its operation. Probing and testing interfaces, which may be temporary connected to a chip or an integrated circuit, can also be subject to stresses at the connection points. Each chip in the 3D integrated circuit can also have irregularities in shape, making interconnection problematic. Specialization of interconnects can help to alleviate these issues.